Memory devices, such as random access memory (RAM), read-only memory (ROM), non-volatile memory (NVM) and like, are known in the art. These devices provide an indication of the data which is stored therein by providing an output electrical signal. A device called a sense amplifier is used for detecting the signal and determining the logical content thereof. U.S. Pat. No. 4,916,671 to Ichiguchi describes one such sense amplifier.
In general, prior art sense amplifiers determine the logical value stored in a cell by comparing the output of the cell with a fixed reference voltage level. The aforementioned U.S. Pat. No. 6,134,156 and 6,128,226 describe an alternative circuit architecture in which a reference cell is used to generate a reference signal in lieu of a fixed reference voltage value.
When a memory cell is programmed or erased, the signal it generates differs from the reference signal by some margin. Since reading the cell's state should always result the same (i.e., either programmed or erased depending on the cell's state), introducing such margin is necessary to overcome imperfections in the reading process and to compensate for drifts in the cell's threshold voltage (e.g., caused by retention loss or disturbs). A reduction in the original margin due to imperfections in the reading process (e.g., due to operation at different operational conditions) is referred to as “margin loss.”
It is well understood that the placement of a reference signal to which an array cell signal can be compared during sensing can be achieved in a number of ways. When close to ground signals are sensed as in the aforementioned U.S. Pat. Nos. 6,134,156 and 6,128,226 patents, the reference cell signal develops at an intermediate rate between that of a programmed cell and an erased cell. When set this way, the array cells' signals on one side of the reference signal are determined to be programmed cells, while signals on the other side of the reference signal are determined to be erased cells. For example, array cells generating signals smaller than the reference signal are considered to be programmed and array cells generating signals larger than the reference signal are considered to be erased. Conventionally, such placement is achieved by using a reference cell whose current is between the erased and programmed cells' current levels. The reference cell's current level can be controlled by the reference cell's size, its programming level, or its gate voltage level. Furthermore, if voltage signals are used to detect the cells' contents, then the reference signal placement can be controlled by providing a different load capacitance on the reference cell compared to that of the array cells. However, if the array and the reference cells differ in their sizes, in their operating gate voltages, or in their loads then some margin loss will be introduced to the sensing scheme. On the other hand, placing the reference cells' signals by properly programming the reference cells (while operating the array and reference cells at identical conditions) minimizes the sensing scheme sensitivity to operating conditions, process parameters and environmental conditions variations, thereby minimizing the margin loss, if any, that is introduced to the sensing system.
When reference cell placement is by programming, it must be programmed a precise amount in order to achieve its intended purpose. There are difficulties attendant with reliable programming of a reference cell so as to minimize operating margin loss, as well as accurate placement of a programmed reference cell relative to the memory array cells. The present invention provides a method for programming reference cells to minimize margin loss and maximize cycling performance.